1.1 --- a/vga.S Sun May 14 13:29:13 2017 +0200
1.2 +++ b/vga.S Sun May 14 23:41:30 2017 +0200
1.3 @@ -23,10 +23,8 @@
1.4 #define LINE_LENGTH 160 /* pixels */
1.5
1.6 #define HFREQ_LIMIT 1254 /* 40MHz cycles */
1.7 -#define LINE_LIMIT 960 /* 40MHz cycles (3 per byte/pixel) */
1.8 -#define HSYNC_LIMIT 96 /* 40MHz cycles (3 per byte/pixel) */
1.9 -
1.10 -#define HSYNC_START LINE_LIMIT
1.11 +#define HSYNC_START 800 /* 40MHz cycles */
1.12 +#define HSYNC_LIMIT 96 /* 40MHz cycles */
1.13 #define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
1.14
1.15 #define VISIBLE_START 15 /* horizontal lines, back porch end */
1.16 @@ -79,8 +77,13 @@
1.17 */
1.18
1.19 la $v0, BMXCON
1.20 - li $v1, (1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */
1.21 - sw $v1, CLR($v0)
1.22 + lw $v1, 0($v0)
1.23 + li $t8, ~(1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */
1.24 + and $v1, $v1, $t8
1.25 + li $t8, ~0b111 /* BMXCON<2:0> = BMXARB<2:0> = 0 */
1.26 + ori $t8, $t8, 0b010 /* BMXCON<2:0> = BMXARB<2:0> = 2 */
1.27 + and $v1, $v1, $t8
1.28 + sw $v1, 0($v0)
1.29
1.30 /* Enable caching. */
1.31