1.1 --- a/mips.h Mon May 15 01:45:09 2017 +0200
1.2 +++ b/mips.h Mon May 15 14:52:17 2017 +0200
1.3 @@ -52,7 +52,8 @@
1.4 #define TLB_ALL_READ (TLB_CACHED | TLB_VALID | TLB_GLOBAL)
1.5 #define TLB_ALL_WRITE (TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL)
1.6
1.7 -#define CONFIG_CM_UNCACHED 2
1.8 -#define CONFIG_CM_CACHABLE_NONCOHERENT 3
1.9 +#define CONFIG_K0 0x00000007
1.10 +#define CONFIG_K0_UNCACHED 2
1.11 +#define CONFIG_K0_CACHABLE_NONCOHERENT 3
1.12
1.13 #endif /* __MIPS_H__ */
2.1 --- a/vga.S Mon May 15 01:45:09 2017 +0200
2.2 +++ b/vga.S Mon May 15 14:52:17 2017 +0200
2.3 @@ -87,8 +87,11 @@
2.4
2.5 /* Enable caching. */
2.6
2.7 - li $v0, CONFIG_CM_CACHABLE_NONCOHERENT
2.8 - mtc0 $v0, CP0_CONFIG
2.9 + mfc0 $v1, CP0_CONFIG
2.10 + li $t8, ~CONFIG_K0
2.11 + and $v1, $v1, $t8
2.12 + ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT
2.13 + mtc0 $v1, CP0_CONFIG
2.14 nop
2.15
2.16 /* Get the RAM size. */