3.1 --- a/vga.S Fri Nov 17 17:22:46 2017 +0100
3.2 +++ b/vga.S Sat Nov 18 17:53:12 2017 +0100
3.3 @@ -115,7 +115,7 @@
3.4 li $t1, (1 << 3) /* PORTA<3> = RA3 */
3.5 sw $t1, CLR($t0)
3.6
3.7 - jal init_oc_pins
3.8 + jal init_io_pins
3.9 nop
3.10
3.11 /* Initialise the status register. */
3.12 @@ -146,6 +146,11 @@
3.13 jal init_oc
3.14 nop
3.15
3.16 + /* Initialise UART for debugging. */
3.17 +
3.18 + jal init_uart
3.19 + nop
3.20 +
3.21 /* Initialise the display state. */
3.22
3.23 li $s0, 0 /* line counter */
3.24 @@ -186,6 +191,10 @@
3.25 li $t1, (1 << 3) /* PORTA<3> = RA3 */
3.26 sw $t1, INV($t0)
3.27
3.28 + la $v0, U1TXREG
3.29 + li $v1, '.'
3.30 + sw $v1, 0($v0)
3.31 +
3.32 bnez $a1, loop /* until counter == 0 */
3.33 nop
3.34
3.35 @@ -374,7 +383,7 @@
3.36 jr $ra
3.37 nop
3.38
3.39 -init_oc_pins:
3.40 +init_io_pins:
3.41 /* Unlock the configuration register bits. */
3.42
3.43 la $v0, SYSKEY
3.44 @@ -401,6 +410,12 @@
3.45 li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */
3.46 sw $v1, 0($v0)
3.47
3.48 + /* Map U1TX to RPB15. */
3.49 +
3.50 + la $v0, RPB15R
3.51 + li $v1, 0b0001 /* RPB15R<3:0> = 0001 (U1TX) */
3.52 + sw $v1, 0($v0)
3.53 +
3.54 la $v0, CFGCON
3.55 sw $t8, 0($v0)
3.56
3.57 @@ -612,6 +627,34 @@
3.58
3.59
3.60
3.61 +/* UART initialisation. */
3.62 +
3.63 +init_uart:
3.64 + /* Initialise UART. */
3.65 +
3.66 + la $v0, U1BRG
3.67 + li $v1, 12 /* U1BRG<15:0> = BRG = (FPB / (16 * baudrate)) - 1 = (24000000 / (16 * 115200)) - 1 = 12 */
3.68 + sw $v1, 0($v0)
3.69 +
3.70 + la $v0, U1MODE
3.71 + li $v1, (1 << 15) /* U1MODE<15> = ON = 0 */
3.72 + sw $v1, CLR($v0)
3.73 +
3.74 + /* Start UART. */
3.75 +
3.76 + la $v0, U1STA
3.77 + li $v1, (1 << 10) /* U1STA<10> = UTXEN = 1 */
3.78 + sw $v1, SET($v0)
3.79 +
3.80 + la $v0, U1MODE
3.81 + li $v1, (1 << 15) /* U1MODE<15> = ON = 1 */
3.82 + sw $v1, SET($v0)
3.83 +
3.84 + jr $ra
3.85 + nop
3.86 +
3.87 +
3.88 +
3.89 /* Utilities. */
3.90
3.91 handle_error_level:
3.92 @@ -796,44 +839,38 @@
3.93
3.94
3.95
3.96 +/* Exception handler. */
3.97 +
3.98 exc_handler:
3.99 - li $t9, 0x80000000
3.100 - mfc0 $t6, CP0_ERROREPC
3.101 + mfc0 $t7, CP0_ERROREPC
3.102 nop
3.103 +
3.104 +exc_write_word:
3.105 + li $t8, 32
3.106 + la $v0, U1TXREG
3.107 exc_loop:
3.108 - and $t7, $t9, $t6
3.109 - beqz $t7, exc_errorepc_zero
3.110 - nop
3.111 -exc_errorepc_one:
3.112 - la $v0, PORTA
3.113 - li $v1, (1 << 2) /* PORTA<2> = RA2 */
3.114 - sw $v1, SET($v0)
3.115 - j exc_loop_wait
3.116 + addiu $t8, $t8, -4
3.117 + srlv $v1, $t7, $t8 /* $v1 = $t7 >> $t8 */
3.118 + andi $v1, $v1, 0xF
3.119 + addiu $t9, $v1, -10 /* $t9 >= 10? */
3.120 + bgez $t9, exc_alpha
3.121 nop
3.122 -exc_errorepc_zero:
3.123 - la $v0, PORTA
3.124 - li $v1, (1 << 3) /* PORTA<3> = RA3 */
3.125 - sw $v1, SET($v0)
3.126 -exc_loop_wait:
3.127 - li $t8, 5000000
3.128 -exc_loop_delay:
3.129 - addiu $t8, $t8, -1
3.130 - bnez $t8, exc_loop_delay
3.131 +exc_digit:
3.132 + addiu $v1, $v1, 48 /* convert to digit: '0' */
3.133 + j exc_write
3.134 nop
3.135 - la $v0, PORTA
3.136 - li $v1, (3 << 2) /* PORTA<3:2> = RA3, RA2 */
3.137 - sw $v1, CLR($v0)
3.138 -exc_loop_wait_again:
3.139 - li $t8, 2500000
3.140 -exc_loop_delay_again:
3.141 - addiu $t8, $t8, -1
3.142 - bnez $t8, exc_loop_delay_again
3.143 +exc_alpha:
3.144 + addiu $v1, $v1, 55 /* convert to alpha: 'A' - 10 */
3.145 +exc_write:
3.146 + sw $v1, 0($v0)
3.147 + bnez $t8, exc_loop
3.148 nop
3.149 -exc_errorepc_next:
3.150 - srl $t9, $t9, 1
3.151 - bnez $t9, exc_loop
3.152 - nop
3.153 - j exc_handler
3.154 +exc_loop_end:
3.155 + li $v1, '\n'
3.156 + sw $v1, 0($v0)
3.157 +
3.158 +exc_handler_end:
3.159 + j exc_handler_end
3.160 nop
3.161
3.162