1.1 --- a/vga.S Sat Jun 03 22:53:06 2017 +0200
1.2 +++ b/vga.S Fri Sep 29 22:10:11 2017 +0200
1.3 @@ -69,8 +69,14 @@
1.4
1.5 la $v0, BMXCON
1.6 lw $v1, 0($v0)
1.7 +
1.8 + /* Set zero wait states for address setup. */
1.9 +
1.10 li $t8, ~(1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */
1.11 and $v1, $v1, $t8
1.12 +
1.13 + /* Set bus arbitration mode. */
1.14 +
1.15 li $t8, ~0b111 /* BMXCON<2:0> = BMXARB<2:0> = 0 */
1.16 ori $t8, $t8, 0b010 /* BMXCON<2:0> = BMXARB<2:0> = 2 */
1.17 and $v1, $v1, $t8
1.18 @@ -307,7 +313,8 @@
1.19 suitable start and end values.
1.20
1.21 Using OC2, Timer 2 triggers a level shifting event and OC2 is reconfigured to
1.22 -reverse the level at a later point.
1.23 +reverse the level at a later point. In this way, the vsync pulse is generated
1.24 +and is synchronised to the display lines.
1.25 */
1.26
1.27 init_oc:
1.28 @@ -369,7 +376,6 @@
1.29 jr $ra
1.30 nop
1.31
1.32 -
1.33 init_oc_pins:
1.34 /* Unlock the configuration register bits. */
1.35
1.36 @@ -718,8 +724,8 @@
1.37 sw $v1, CLR($v0)
1.38
1.39 /*
1.40 - The timer interrupt will only occur active outside the visible region,
1.41 - but the interrupt condition will still occur as the timer wraps around.
1.42 + The timer interrupt will only occur outside the visible region, but the
1.43 + interrupt condition will still occur as the timer wraps around.
1.44 Therefore, the handling of other interrupts may find the timer interrupt
1.45 condition set.
1.46
1.47 @@ -881,10 +887,10 @@
1.48 la $v0, DCH0SSA
1.49 sw $s2, 0($v0)
1.50
1.51 - /* Enable the line channel. */
1.52 + /* Enable the line channel for timer event transfer initiation. */
1.53
1.54 la $v0, DCH0ECON
1.55 - li $v1, (1 << 4)
1.56 + li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
1.57 sw $v1, SET($v0)
1.58
1.59 /* Disable the timer interrupt during the visible period. */
1.60 @@ -943,7 +949,7 @@
1.61 /* Disable the line channel. */
1.62
1.63 la $v0, DCH0ECON
1.64 - li $v1, (1 << 4)
1.65 + li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */
1.66 sw $v1, CLR($v0)
1.67
1.68 j _visible_update_ret