1.1 --- a/vga.S Tue May 16 16:49:25 2017 +0200
1.2 +++ b/vga.S Tue May 16 17:58:26 2017 +0200
1.3 @@ -22,9 +22,9 @@
1.4
1.5 #define LINE_LENGTH 160 /* pixels */
1.6
1.7 -#define HFREQ_LIMIT 1254 /* 40MHz cycles */
1.8 -#define HSYNC_START 800 /* 40MHz cycles */
1.9 -#define HSYNC_LIMIT 96 /* 40MHz cycles */
1.10 +#define HFREQ_LIMIT 936 /* 30MHz cycles */
1.11 +#define HSYNC_START 800 /* 30MHz cycles */
1.12 +#define HSYNC_LIMIT 112 /* 30MHz cycles */
1.13 #define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
1.14
1.15 #define VISIBLE_START 15 /* horizontal lines, back porch end */
1.16 @@ -57,14 +57,14 @@
1.17
1.18 /*
1.19 Set the FRC oscillator PLL function with an input division of 4, an output
1.20 -division of 2, a multiplication of 20, yielding a multiplication of 2.5.
1.21 +division of 2, a multiplication of 15, yielding a multiplication of 1.875.
1.22
1.23 -The FRC is apparently at 16MHz and this produces a system clock of 40MHz.
1.24 +The FRC is apparently at 16MHz and this produces a system clock of 30MHz.
1.25 */
1.26
1.27 .section .devcfg2, "a"
1.28 -.word 0xfff9ffdb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.29 - DEVCFG2<6:4> = FPLLMUL<2:0> = 101;
1.30 +.word 0xfff9ff8b /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.31 + DEVCFG2<6:4> = FPLLMUL<2:0> = 000;
1.32 DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
1.33
1.34 .text