1.1 --- a/vga.S Wed May 17 23:53:40 2017 +0200
1.2 +++ b/vga.S Thu May 18 00:25:51 2017 +0200
1.3 @@ -22,15 +22,15 @@
1.4
1.5 #define LINE_LENGTH 160 /* pixels */
1.6
1.7 -#define HFREQ_LIMIT 936 /* 30MHz cycles */
1.8 -#define HSYNC_START 800 /* 30MHz cycles */
1.9 -#define HSYNC_LIMIT 112 /* 30MHz cycles */
1.10 +#define HFREQ_LIMIT 643 /* 24MHz cycles */
1.11 +#define HSYNC_START 460 /* 24MHz cycles */
1.12 +#define HSYNC_LIMIT 64 /* 24MHz cycles */
1.13 #define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
1.14
1.15 -#define VISIBLE_START 15 /* horizontal lines, back porch end */
1.16 -#define VFP_START 527 /* horizontal lines, front porch start */
1.17 -#define VSYNC_START 529 /* horizontal lines, front porch end */
1.18 -#define VSYNC_END 531 /* horizontal lines, back porch start */
1.19 +#define VISIBLE_START 70 /* horizontal lines, back porch end */
1.20 +#define VFP_START 592 /* horizontal lines, front porch start */
1.21 +#define VSYNC_START 620 /* horizontal lines, front porch end */
1.22 +#define VSYNC_END 622 /* horizontal lines, back porch start */
1.23
1.24 #define SCREEN_SIZE (40 * 1024)
1.25
1.26 @@ -41,9 +41,7 @@
1.27
1.28 /*
1.29 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.30 -divided by 1, and FRCDIV+PLL selected.
1.31 -
1.32 -The system clock and peripheral clock are therefore the same.
1.33 +divided by 2, and FRCDIV+PLL selected.
1.34
1.35 The watchdog timer (FWDTEN) is also disabled.
1.36
1.37 @@ -52,19 +50,19 @@
1.38 */
1.39
1.40 .section .devcfg1, "a"
1.41 -.word 0xff7fcfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 0;
1.42 +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.43 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.44
1.45 /*
1.46 Set the FRC oscillator PLL function with an input division of 4, an output
1.47 -division of 2, a multiplication of 15, yielding a multiplication of 1.875.
1.48 -
1.49 -The FRC is apparently at 16MHz and this produces a system clock of 30MHz.
1.50 +division of 2, a multiplication of 24, yielding a multiplication of 3.
1.51 +
1.52 +The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
1.53 */
1.54
1.55 .section .devcfg2, "a"
1.56 -.word 0xfff9ff8b /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.57 - DEVCFG2<6:4> = FPLLMUL<2:0> = 000;
1.58 +.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.59 + DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
1.60 DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
1.61
1.62 .text