2.1 --- a/vga.S Fri Nov 03 23:25:06 2017 +0100
2.2 +++ b/vga.S Tue Nov 07 14:04:29 2017 +0100
2.3 @@ -284,8 +284,6 @@
2.4 la $v0, IPC2
2.5 li $v1, 0b11111
2.6 sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
2.7 -
2.8 - la $v0, IPC2
2.9 li $v1, 0b11111
2.10 sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
2.11
2.12 @@ -628,6 +626,7 @@
2.13 mfc0 $t3, CP0_STATUS
2.14 li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */
2.15 and $t3, $t3, $t4
2.16 + ori $t3, $t3, (3 << STATUS_IRQ_SHIFT)
2.17 li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
2.18 and $t3, $t3, $t4
2.19 ori $t3, $t3, STATUS_IE
2.20 @@ -890,12 +889,25 @@
2.21 li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
2.22 sw $v1, SET($v0)
2.23
2.24 - /* Disable the timer interrupt during the visible period. */
2.25 + /*
2.26 + Suspend delivery of the timer interrupt during the visible period.
2.27 + The condition still occurs, however.
2.28 + */
2.29
2.30 la $v0, IEC0
2.31 li $v1, (1 << 9)
2.32 sw $v1, CLR($v0) /* T2IE = 0 */
2.33
2.34 + la $v0, IPC2
2.35 + li $v1, 0b11111
2.36 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
2.37 + li $v1, 0b00111
2.38 + sw $v1, SET($v0) /* T2IP = 1; T2IS = 3 */
2.39 +
2.40 + la $v0, IEC0
2.41 + li $v1, (1 << 9)
2.42 + sw $v1, SET($v0) /* T2IE = 0 */
2.43 +
2.44 _vbp_active_ret:
2.45 jr $ra
2.46 nop
2.47 @@ -915,7 +927,17 @@
2.48
2.49 la $s1, vfp_active
2.50
2.51 - /* Re-enable the timer interrupt after the visible period. */
2.52 + /* Restore delivery of the timer interrupt after the visible period. */
2.53 +
2.54 + la $v0, IEC0
2.55 + li $v1, (1 << 9)
2.56 + sw $v1, CLR($v0) /* T2IE = 0 */
2.57 +
2.58 + la $v0, IPC2
2.59 + li $v1, 0b11111
2.60 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
2.61 + li $v1, 0b11111
2.62 + sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
2.63
2.64 la $v0, IEC0
2.65 li $v1, (1 << 9)