1.1 --- a/vga.S Fri Nov 03 01:20:19 2017 +0100
1.2 +++ b/vga.S Fri Nov 03 20:31:05 2017 +0100
1.3 @@ -429,13 +429,13 @@
1.4 /* Disable DMA interrupts. */
1.5
1.6 la $v0, IEC1
1.7 - li $v1, (3 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 0 */
1.8 + li $v1, (0b111 << 28) /* IEC1<30:28> = DMA2IE, DMA1IE, DMA0IE = 0 */
1.9 sw $v1, CLR($v0)
1.10
1.11 /* Clear DMA interrupt flags. */
1.12
1.13 la $v0, IFS1
1.14 - li $v1, (3 << 28) /* IFS1<29:28> = DMA1IF, DMA0IF = 0 */
1.15 + li $v1, (0b111 << 28) /* IFS1<30:28> = DMA2IF, DMA1IF, DMA0IF = 0 */
1.16 sw $v1, CLR($v0)
1.17
1.18 /* Enable DMA. */
1.19 @@ -446,7 +446,7 @@
1.20
1.21 /*
1.22 Initialise a line channel.
1.23 - The line channel will be channel 0 (x = 0).
1.24 + The line channel will be channel 1 (x = 1).
1.25
1.26 Specify a priority of 3:
1.27 DCHxCON<1:0> = CHPRI<1:0> = 3
1.28 @@ -455,13 +455,13 @@
1.29 DCHxCON<4> = CHAEN = 1
1.30 */
1.31
1.32 - la $v0, DCH0CON
1.33 + la $v0, DCH1CON
1.34 li $v1, 0b10011
1.35 sw $v1, 0($v0)
1.36
1.37 /*
1.38 Initialise a level reset channel.
1.39 - The reset channel will be channel 1 (x = 1).
1.40 + The reset channel will be channel 2 (x = 2).
1.41
1.42 Specify a priority of 3:
1.43 DCHxCON<1:0> = CHPRI<1:0> = 3
1.44 @@ -473,7 +473,7 @@
1.45 DCHxCON<6> = CHAED = 1
1.46 */
1.47
1.48 - la $v0, DCH1CON
1.49 + la $v0, DCH2CON
1.50 li $v1, 0b1100011
1.51 sw $v1, 0($v0)
1.52
1.53 @@ -486,18 +486,18 @@
1.54 For now, however, prevent initiation by not setting SIRQEN.
1.55 */
1.56
1.57 - la $v0, DCH0ECON
1.58 + la $v0, DCH1ECON
1.59 li $v1, (9 << 8)
1.60 sw $v1, 0($v0)
1.61
1.62 /*
1.63 - Initiate reset channel transfer when channel 0 is finished:
1.64 - DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt
1.65 + Initiate reset channel transfer when channel 1 is finished:
1.66 + DCHxECON<15:8> = CHSIRQ<7:0> = channel 1 interrupt
1.67 DCHxECON<4> = SIRQEN = 1
1.68 */
1.69
1.70 - la $v0, DCH1ECON
1.71 - li $v1, (60 << 8) | (1 << 4)
1.72 + la $v0, DCH2ECON
1.73 + li $v1, (61 << 8) | (1 << 4)
1.74 sw $v1, 0($v0)
1.75
1.76 /*
1.77 @@ -505,7 +505,7 @@
1.78 DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH
1.79 */
1.80
1.81 - la $v0, DCH0CSIZ
1.82 + la $v0, DCH1CSIZ
1.83 li $v1, LINE_LENGTH
1.84 sw $v1, 0($v0)
1.85
1.86 @@ -514,7 +514,7 @@
1.87 DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1
1.88 */
1.89
1.90 - la $v0, DCH1CSIZ
1.91 + la $v0, DCH2CSIZ
1.92 li $v1, 1
1.93 sw $v1, 0($v0)
1.94
1.95 @@ -523,11 +523,11 @@
1.96 DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1
1.97 */
1.98
1.99 - la $v0, DCH0SSIZ
1.100 + la $v0, DCH1SSIZ
1.101 li $v1, LINE_LENGTH
1.102 sw $v1, 0($v0)
1.103
1.104 - la $v0, DCH1SSIZ
1.105 + la $v0, DCH2SSIZ
1.106 li $v1, 1
1.107 sw $v1, 0($v0)
1.108
1.109 @@ -536,7 +536,7 @@
1.110 DCHxSSA = physical(line data address)
1.111 */
1.112
1.113 - la $v0, DCH0SSA
1.114 + la $v0, DCH1SSA
1.115 li $v1, SCREEN_BASE
1.116 sw $v1, 0($v0)
1.117
1.118 @@ -545,7 +545,7 @@
1.119 DCHxSSA = physical(zero data address)
1.120 */
1.121
1.122 - la $v0, DCH1SSA
1.123 + la $v0, DCH2SSA
1.124 la $v1, zerodata
1.125 li $t8, KSEG0_BASE
1.126 subu $v1, $v1, $t8
1.127 @@ -556,11 +556,11 @@
1.128 DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1
1.129 */
1.130
1.131 - la $v0, DCH0DSIZ
1.132 + la $v0, DCH1DSIZ
1.133 li $v1, 1
1.134 sw $v1, 0($v0)
1.135
1.136 - la $v0, DCH1DSIZ
1.137 + la $v0, DCH2DSIZ
1.138 sw $v1, 0($v0)
1.139
1.140 /*
1.141 @@ -568,13 +568,13 @@
1.142 DCHxDSA = physical(PORTB)
1.143 */
1.144
1.145 - la $v0, DCH0DSA
1.146 + la $v0, DCH1DSA
1.147 li $v1, PORTB
1.148 li $t8, KSEG1_BASE
1.149 subu $v1, $v1, $t8
1.150 sw $v1, 0($v0)
1.151
1.152 - la $v0, DCH1DSA
1.153 + la $v0, DCH2DSA
1.154 sw $v1, 0($v0)
1.155
1.156 /*
1.157 @@ -582,27 +582,27 @@
1.158 address can be updated.
1.159 */
1.160
1.161 - la $v0, DCH0INT
1.162 + la $v0, DCH1INT
1.163 li $v1, (1 << 19) /* CHBCIE = 1 */
1.164 sw $v1, 0($v0)
1.165
1.166 /* Enable interrupt for address updating. */
1.167
1.168 la $v0, IPC10
1.169 - li $v1, 0b11111 /* DMA0IP, DMA0IS = 0 */
1.170 + li $v1, 0b1111100000000 /* DMA1IP, DMA1IS = 0 */
1.171 sw $v1, CLR($v0)
1.172
1.173 la $v0, IPC10
1.174 - li $v1, 0b11111 /* DMA0IP = 7, DMA0IS = 3 */
1.175 + li $v1, 0b1111100000000 /* DMA1IP = 7, DMA1IS = 3 */
1.176 sw $v1, SET($v0)
1.177
1.178 la $v0, IEC1
1.179 - li $v1, (1 << 28) /* IEC1<28> = DMA0IE = 1 */
1.180 + li $v1, (1 << 29) /* IEC1<29> = DMA1IE = 1 */
1.181 sw $v1, SET($v0)
1.182
1.183 /* Enable line channel. */
1.184
1.185 - la $v0, DCH0CON
1.186 + la $v0, DCH1CON
1.187 li $v1, 0b10000000
1.188 sw $v1, SET($v0)
1.189
1.190 @@ -752,19 +752,19 @@
1.191
1.192 la $v0, IFS1
1.193 lw $v1, 0($v0)
1.194 - li $t8, (1 << 28) /* DMA0IF */
1.195 + li $t8, (1 << 29) /* DMA1IF */
1.196 and $v1, $v1, $t8
1.197 beqz $v1, irq_exit
1.198 nop
1.199
1.200 /* Clear the DMA interrupt condition. */
1.201
1.202 - li $v1, (1 << 28) /* IFS1<28> = DMA0IF = 0 */
1.203 + li $v1, (1 << 29) /* IFS1<29> = DMA1IF = 0 */
1.204 sw $v1, CLR($v0)
1.205
1.206 /* Test the block transfer completion interrupt flag. */
1.207
1.208 - la $v0, DCH0INT
1.209 + la $v0, DCH1INT
1.210 lw $v1, 0($v0)
1.211 andi $v1, $v1, (1 << 3) /* CHBCIF */
1.212 beqz $v1, irq_exit
1.213 @@ -884,13 +884,13 @@
1.214
1.215 /* Update the source address. */
1.216
1.217 - la $v0, DCH0SSA
1.218 + la $v0, DCH1SSA
1.219 sw $s2, 0($v0)
1.220
1.221 /* Enable the line channel for timer event transfer initiation. */
1.222
1.223 - la $v0, DCH0ECON
1.224 - li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
1.225 + la $v0, DCH1ECON
1.226 + li $v1, (1 << 4) /* DCH1ECON<4> = SIRQEN = 1 */
1.227 sw $v1, SET($v0)
1.228
1.229 /* Disable the timer interrupt during the visible period. */
1.230 @@ -948,8 +948,8 @@
1.231
1.232 /* Disable the line channel. */
1.233
1.234 - la $v0, DCH0ECON
1.235 - li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */
1.236 + la $v0, DCH1ECON
1.237 + li $v1, (1 << 4) /* DCH1ECON<4> = SIRQEN = 0 */
1.238 sw $v1, CLR($v0)
1.239
1.240 j _visible_update_ret
1.241 @@ -985,18 +985,18 @@
1.242
1.243 /* Disable line channel. */
1.244
1.245 - la $v0, DCH0CON
1.246 + la $v0, DCH1CON
1.247 li $v1, 0b10000000
1.248 sw $v1, CLR($v0)
1.249
1.250 /* Update the source address. */
1.251
1.252 - la $v0, DCH0SSA
1.253 + la $v0, DCH1SSA
1.254 sw $s2, 0($v0)
1.255
1.256 /* Enable line channel. */
1.257
1.258 - la $v0, DCH0CON
1.259 + la $v0, DCH1CON
1.260 sw $v1, SET($v0)
1.261
1.262 _visible_update_ret: