1.1 --- a/vga.S Sat Jun 03 16:26:10 2017 +0200
1.2 +++ b/vga.S Sat Jun 03 19:13:09 2017 +0200
1.3 @@ -711,6 +711,11 @@
1.4 beqz $v1, irq_dma
1.5 nop
1.6
1.7 + /* Clear the timer interrupt condition. */
1.8 +
1.9 + li $v1, (1 << 9) /* IFS0<9> = T2IF = 0 */
1.10 + sw $v1, CLR($v0)
1.11 +
1.12 /* Increment the line counter. */
1.13
1.14 addiu $s0, $s0, 1
1.15 @@ -720,16 +725,7 @@
1.16 jalr $s1
1.17 nop
1.18
1.19 -irq_clear_timer:
1.20 -
1.21 - /* Clear the timer interrupt condition. */
1.22 -
1.23 - la $v0, IFS0
1.24 - li $v1, (1 << 9) /* IFS0<9> = T2IF = 0 */
1.25 - sw $v1, CLR($v0)
1.26 -
1.27 irq_dma:
1.28 -
1.29 /* Check for a DMA interrupt condition. */
1.30
1.31 la $v0, IFS1
1.32 @@ -739,12 +735,17 @@
1.33 beqz $v1, irq_exit
1.34 nop
1.35
1.36 + /* Clear the DMA interrupt condition. */
1.37 +
1.38 + li $v1, (1 << 28) /* IFS1<28> = DMA0IF = 0 */
1.39 + sw $v1, CLR($v0)
1.40 +
1.41 /* Test the block transfer completion interrupt flag. */
1.42
1.43 la $v0, DCH0INT
1.44 lw $v1, 0($v0)
1.45 andi $v1, $v1, (1 << 3) /* CHBCIF */
1.46 - beqz $v1, irq_clear_dma
1.47 + beqz $v1, irq_exit
1.48 nop
1.49
1.50 /* Clear the block transfer completion interrupt flag. */
1.51 @@ -758,7 +759,7 @@
1.52 */
1.53
1.54 andi $t8, $s0, 1
1.55 - bnez $t8, irq_clear_dma
1.56 + bnez $t8, irq_exit
1.57 nop
1.58
1.59 /* Reference the next line and update the DMA source address. */
1.60 @@ -794,14 +795,6 @@
1.61 la $v0, DCH0CON
1.62 sw $v1, SET($v0)
1.63
1.64 -irq_clear_dma:
1.65 -
1.66 - /* Clear the DMA interrupt condition. */
1.67 -
1.68 - la $v0, IFS1
1.69 - li $v1, (1 << 28) /* IFS1<28> = DMA0IF = 0 */
1.70 - sw $v1, CLR($v0)
1.71 -
1.72 irq_exit:
1.73 /* Save state. */
1.74