VGAPIC32

Shortlog

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2018-10-20 Paul Boddie Added tag snapshot-20171120 for changeset c9ec1da2c3ca default tip
2018-10-20 Paul Boddie Added tag snapshot-20171119 for changeset 2bc674143b08
2017-11-20 Paul Boddie Merged changes from a parallel development branch.
2017-11-20 Paul Boddie Enable and disable the DMA channel rather than changing IRQ settings. snapshot-20171120
2017-11-20 Paul Boddie Merged changes from a parallel development branch.
2017-11-20 Paul Boddie Remove superfluous CHAED (receive events when disabled) flag. Minor tidying.
2017-11-20 Paul Boddie Remove apparently superfluous Timer3 interrupt initialisation.
2017-11-20 Paul Boddie Merged changes from a parallel development branch.
2017-11-20 Paul Boddie Remove apparently superfluous Timer2 interrupt initialisation.
2017-11-20 Paul Boddie Merged changes from a parallel development branch. Retained DMA interrupt usage
2017-11-20 Paul Boddie Invoke the display state machine using output compare interrupts instead of a
2017-11-19 Paul Boddie Enable the Timer3 interrupt at low priority.
2017-11-19 Paul Boddie Merged changes from a parallel development branch. The result is still broken.
2017-11-19 Paul Boddie Merged changes from a parallel development branch.
2017-11-19 Paul Boddie Save and restore $gp so that the text blitting functions do not cause crashes. snapshot-20171119
2017-11-18 Paul Boddie Fixed declarations.
2017-11-18 Paul Boddie Moved exception handler to the end.
2017-11-18 Paul Boddie Introduced macros to ensure register saving and loading consistency.
2017-11-18 Paul Boddie Introduced UART usage to obtain exception details.
2017-11-17 Paul Boddie Update timer interrupt priorities atomically, removing disable/enable code.
2017-11-16 Paul Boddie Reorganised interrupt handling to only test either timer or DMA interrupt
2017-11-07 Paul Boddie Reordered channel and timer activation instructions, tidied generally.
2017-11-07 Paul Boddie Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
2017-11-07 Paul Boddie Reordered channel and timer activation instructions, tidied generally.
2017-11-07 Paul Boddie Reordered channel and timer activation instructions, tidied generally.
2017-11-07 Paul Boddie Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
2017-11-07 Paul Boddie Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
2017-11-06 Paul Boddie Enable Timer3 interrupts in order to create timer events.
2017-11-06 Paul Boddie Double the peripheral clock frequency for further timer usage.
2017-11-06 Paul Boddie Removed superfluous interrupt handling.
2017-11-06 Paul Boddie Disabled the reset channel interrupt which appears superfluous for chaining as
2017-11-06 Paul Boddie Test usage of Timer3 to initiate the reset channel cell transfer.
2017-11-06 Paul Boddie Test usage of Timer3 to initiate the reset channel cell transfer.
2017-11-06 Paul Boddie Test usage of Timer3 to initiate the reset channel cell transfer.
2017-11-04 Paul Boddie A tentative sketch of how OC3 might drive line DMA transfers and the clock pulse
2017-11-04 Paul Boddie Make DMA channel 1 the line channel. Things will only now work if the Timer2
2017-11-04 Paul Boddie Test chaining of DMA channels, adding one between the line and reset channels.
2017-11-04 Paul Boddie Make DMA channel 1 the line channel. Things will only now work if the Timer2 CLKO-to-74HC273-CP
2017-11-04 Paul Boddie Test chaining of DMA channels, adding one between the line and reset channels. CLKO-to-74HC273-CP
2017-11-04 Paul Boddie Simplify REFCLKO initialisation and set RODIV to 2 to test pixel uniformity. CLKO-to-74HC273-CP
2017-11-04 Paul Boddie Switch to REFCLKO instead of using CLKO and the primary oscillator. CLKO-to-74HC273-CP
2017-11-04 Paul Boddie Experiment with the use of CLKO providing the clock pulse of a flip-flop CLKO-to-74HC273-CP
2017-11-03 Paul Boddie Removed redundant operations such as loads whose values are already loaded.
2017-11-03 Paul Boddie Removed redundant operations such as loads whose values are already loaded.
2017-11-03 Paul Boddie Change the DMA channels used from 0 and 1 to 1 and 2.
2017-11-03 Paul Boddie Fixed DMA channel 2 registers. Reformatted and added some more definitions.
2017-11-03 Paul Boddie Fixed comments.
2017-09-29 Paul Boddie Added some comments.
2017-06-03 Paul Boddie Disable the timer interrupt in order to reduce memory contention with the line
2017-06-03 Paul Boddie Disable the line channel only when its completion is being handled.
2017-06-03 Paul Boddie Created a separate DMA address update routine. Note that it does not use $ra
2017-06-03 Paul Boddie Simplified the interrupt handler slightly.
2017-06-03 Paul Boddie Reset the DMA source address for the first line, even though it is not necessary
2017-06-03 Paul Boddie Disable and re-enable the line channel when setting the source address, even
2017-05-30 Paul Boddie Put character string, font and image data into separate files.
2017-05-30 Paul Boddie Added a tool to generate font definitions from GNU Unifont definitions.
2017-05-28 Paul Boddie Transition between the picture and the pattern.
2017-05-28 Paul Boddie Added register and display state saving and retrieval in the interrupt handler.
2017-05-28 Paul Boddie Write to KSEG0 instead of KSEG1.
2017-05-28 Paul Boddie Moved the framebuffer copying routine into a separate function.
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