1 /* 2 * Ben NanoNote and Arduino USB Host shield communication. 3 * 4 * Copyright 2013 Paul Boddie 5 * 6 * SPI functions derived from those in lib/atben.c by Werner Almesberger: 7 * 8 * Copyright 2010-2011 Werner Almesberger 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #include <ubb/ubb.h> 17 #include <stdio.h> 18 #include <signal.h> 19 #include <stdlib.h> 20 #include <usb.h> 21 #include <unistd.h> 22 #include <string.h> 23 24 /* Found in Python's asdl.h. */ 25 26 #ifndef __cplusplus 27 typedef enum {false, true} bool; 28 #endif 29 30 /* Initialisation states. */ 31 32 typedef enum 33 { 34 MAX_DEVSTATE_INIT = 0, 35 MAX_DEVSTATE_CONNECTED = 1, 36 MAX_DEVSTATE_RESET = 2, 37 MAX_DEVSTATE_INSPECTED = 3, 38 MAX_DEVSTATE_RESET_AGAIN = 4, 39 MAX_DEVSTATE_READY = 5 40 } max_devstate; 41 42 /* Device details. */ 43 44 typedef struct 45 { 46 bool in_toggle, out_toggle; 47 struct usb_device_descriptor desc; 48 } max_device; 49 50 /* Pin assignments: 51 * 52 * Sniffer UBB Shield 53 * ------- ---- ------ 54 * DAT2 DAT2 9 (INT) 55 * CD DAT3 10 (SS) 56 * CMD CMD 7 (RESET) 57 * VCC VDD VIN 58 * CLK CLK 13 (SCLK) 59 * GND GND GND 60 * DAT0 DAT0 11 (MOSI) 61 * DAT1 DAT1 12 (MISO) 62 * 8 (GPX) (not assigned) 63 */ 64 65 #define MAX_RESET UBB_CMD 66 #define MAX_SCLK UBB_CLK 67 #define MAX_MOSI UBB_DAT0 68 #define MAX_MISO UBB_DAT1 69 #define MAX_INT UBB_DAT2 70 #define MAX_SS UBB_DAT3 71 72 /* MAX3421E definitions. */ 73 74 #define MAX_REG_READ 0x00 75 #define MAX_REG_WRITE 0x02 76 77 #define MAX_REG_RCVFIFO 1 78 #define MAX_REG_SNDFIFO 2 79 #define MAX_REG_SUDFIFO 4 80 #define MAX_REG_RCVBC 6 81 #define MAX_REG_SNDBC 7 82 #define MAX_REG_USBIRQ 13 83 #define MAX_REG_USBIEN 14 84 #define MAX_REG_USBCTL 15 85 #define MAX_REG_CPUCTL 16 86 #define MAX_REG_PINCTL 17 87 #define MAX_REG_REVISION 18 88 #define MAX_REG_HIRQ 25 89 #define MAX_REG_HIEN 26 90 #define MAX_REG_MODE 27 91 #define MAX_REG_PERADDR 28 92 #define MAX_REG_HCTL 29 93 #define MAX_REG_HXFR 30 94 #define MAX_REG_HRSL 31 95 96 #define MAX_USBIRQ_OSCOKIRQ 1 97 #define MAX_USBIRQ_NOVBUSIRQ 32 98 #define MAX_USBIRQ_VBUSIRQ 64 99 100 #define MAX_USBCTL_PWRDOWN 16 101 #define MAX_USBCTL_CHIPRES 32 102 103 #define MAX_CPUCTL_IE 1 104 105 #define MAX_PINCTL_POSINT_LOW 0 106 #define MAX_PINCTL_POSINT_HIGH 4 107 #define MAX_PINCTL_INTLEVEL_EDGE 0 108 #define MAX_PINCTL_INTLEVEL_LEVEL 8 109 #define MAX_PINCTL_FDUPSPI_HALF 0 110 #define MAX_PINCTL_FDUPSPI_FULL 16 111 112 #define MAX_HIRQ_BUSEVENTIRQ 1 113 #define MAX_HIRQ_RWUIRQ 2 114 #define MAX_HIRQ_RCVDAVIRQ 4 115 #define MAX_HIRQ_SNDBAVIRQ 8 116 #define MAX_HIRQ_SUSDNIRQ 16 117 #define MAX_HIRQ_CONDETIRQ 32 118 #define MAX_HIRQ_FRAMEIRQ 64 119 #define MAX_HIRQ_HXFRDNIRQ 128 120 121 #define MAX_HIEN_BUSEVENTIE 1 122 #define MAX_HIEN_CONDETIE 32 123 #define MAX_HIEN_FRAMEIE 64 124 125 #define MAX_MODE_PERIPHERAL 0 126 #define MAX_MODE_HOST 1 127 #define MAX_MODE_LOWSPEED 2 128 #define MAX_MODE_SOFKAENAB 8 129 #define MAX_MODE_SEPIRQ_OFF 0 130 #define MAX_MODE_SEPIRQ_ON 16 131 #define MAX_MODE_DMPULLDN 64 132 #define MAX_MODE_DPPULLDN 128 133 134 #define MAX_MODE_HOST_ENABLED MAX_MODE_HOST | MAX_MODE_SEPIRQ_OFF | MAX_MODE_DMPULLDN | MAX_MODE_DPPULLDN 135 #define MAX_MODE_HOST_FULLSPEED MAX_MODE_HOST_ENABLED 136 #define MAX_MODE_HOST_LOWSPEED MAX_MODE_HOST_ENABLED | MAX_MODE_LOWSPEED 137 138 #define MAX_HCTL_BUSRST 1 139 #define MAX_HCTL_SAMPLEBUS 4 140 #define MAX_HCTL_RCVTOG0 16 141 #define MAX_HCTL_RCVTOG1 32 142 #define MAX_HCTL_SNDTOG0 64 143 #define MAX_HCTL_SNDTOG1 128 144 145 #define MAX_HXFR_SETUP 16 146 #define MAX_HXFR_OUTNIN 32 147 #define MAX_HXFR_HS 128 148 149 #define MAX_HRSL_JSTATUS 128 150 #define MAX_HRSL_KSTATUS 64 151 #define MAX_HRSL_SNDTOGRD 32 152 #define MAX_HRSL_RCVTOGRD 16 153 #define MAX_HRSL_HRSLT 15 154 155 #define max_reg(n) ((uint8_t) (n << 3)) 156 #define max_reg_read(n) (max_reg(n) | MAX_REG_READ) 157 #define max_reg_write(n) (max_reg(n) | MAX_REG_WRITE) 158 159 void spi_begin() 160 { 161 CLR(MAX_SS); 162 } 163 164 void spi_end() 165 { 166 SET(MAX_SS); 167 } 168 169 /** 170 * Send the given value via MOSI while receiving a value via MISO. 171 * This requires full-duplex SPI and will produce a status value for the first 172 * value sent (the command). 173 */ 174 uint8_t spi_sendrecv(uint8_t v) 175 { 176 uint8_t result = 0; 177 uint8_t mask; 178 179 for (mask = 0x80; mask; mask >>= 1) 180 { 181 if (v & mask) 182 { 183 #ifdef DEBUG 184 printf("1"); 185 #endif 186 SET(MAX_MOSI); 187 } 188 else 189 { 190 #ifdef DEBUG 191 printf("0"); 192 #endif 193 CLR(MAX_MOSI); 194 } 195 196 /* Wait for stable output signal. */ 197 198 SET(MAX_SCLK); 199 200 if (PIN(MAX_MISO)) 201 result |= mask; 202 203 CLR(MAX_SCLK); 204 } 205 206 #ifdef DEBUG 207 printf("\n"); 208 #endif 209 return result; 210 } 211 212 uint8_t max_read(uint8_t reg, uint8_t *status) 213 { 214 uint8_t result = 0, tmpstatus = 0; 215 216 tmpstatus = 0; 217 218 spi_begin(); 219 tmpstatus = spi_sendrecv(max_reg_read(reg)); 220 result = spi_sendrecv(0); 221 spi_end(); 222 223 if (status != NULL) 224 *status = tmpstatus; 225 226 return result; 227 } 228 229 uint8_t max_write(uint8_t reg, uint8_t value) 230 { 231 uint8_t status = 0; 232 233 spi_begin(); 234 status = spi_sendrecv(max_reg_write(reg)); 235 spi_sendrecv(value); 236 spi_end(); 237 238 return status; 239 } 240 241 /** 242 * Return whether data can be sent. 243 */ 244 bool max_can_send(uint8_t *status) 245 { 246 if (status == NULL) 247 return max_read(MAX_REG_HIRQ, NULL) & MAX_HIRQ_SNDBAVIRQ; 248 else 249 return *status & MAX_HIRQ_SNDBAVIRQ; 250 } 251 252 /** 253 * Set the sending data toggle. 254 */ 255 void max_set_send_toggle(bool toggle) 256 { 257 max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_SNDTOG1 : MAX_HCTL_SNDTOG0); 258 } 259 260 /** 261 * Return the sending data toggle. 262 */ 263 bool max_get_send_toggle() 264 { 265 return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_SNDTOGRD) != 0; 266 } 267 268 /** 269 * Set the receiving data toggle. 270 */ 271 void max_set_recv_toggle(bool toggle) 272 { 273 max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_RCVTOG1 : MAX_HCTL_RCVTOG0); 274 } 275 276 /** 277 * Return the receiving data toggle. 278 */ 279 bool max_get_recv_toggle() 280 { 281 return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_RCVTOGRD) != 0; 282 } 283 284 /** 285 * Wait for handshake/timeout after a transfer. 286 */ 287 uint8_t max_wait_transfer(uint8_t status) 288 { 289 while (!(status & MAX_HIRQ_HXFRDNIRQ)) 290 { 291 status = max_read(MAX_REG_HIRQ, NULL); 292 } 293 294 return status; 295 } 296 297 /** 298 * Write the given data to the FIFO. 299 */ 300 void max_write_fifo(uint8_t endpoint, uint8_t *data, uint8_t len) 301 { 302 uint8_t count; 303 304 for (count = 0; count < len; count++) 305 { 306 max_write(endpoint ? MAX_REG_SNDFIFO : MAX_REG_SUDFIFO, data[count]); 307 } 308 309 if (endpoint) 310 max_write(MAX_REG_SNDBC, len); 311 } 312 313 /** 314 * Read the data from the FIFO. 315 */ 316 void max_read_fifo(uint8_t *data, uint8_t *len, uint8_t *datalimit) 317 { 318 uint8_t count, received = max_read(MAX_REG_RCVBC, NULL); 319 320 *len += received; 321 322 for (count = 0; (count < received) && (data < datalimit); count++) 323 { 324 *data++ = max_read(MAX_REG_RCVFIFO, NULL); 325 } 326 } 327 328 /** 329 * Send a control request to the given address consisting of the given setup 330 * data. 331 */ 332 uint8_t max_control(uint8_t address, uint8_t *setup) 333 { 334 uint8_t status, hrsl; 335 336 max_write_fifo(0, setup, 8); 337 338 /* Set the address. */ 339 340 max_write(MAX_REG_PERADDR, address); 341 342 /* Initiate the transfer. */ 343 344 do 345 { 346 status = max_write(MAX_REG_HXFR, MAX_HXFR_SETUP); 347 status = max_wait_transfer(status); 348 hrsl = max_read(MAX_REG_HRSL, &status); 349 } 350 while (hrsl & MAX_HRSL_HRSLT); 351 352 return status; 353 } 354 355 /** 356 * Perform a status transaction as part of a larger control transaction. 357 * The out parameter is used to indicate the kind of status transfer to be 358 * performed and should be the inverse of the control transfer direction. 359 */ 360 uint8_t max_control_status(bool out) 361 { 362 uint8_t status, hrsl; 363 364 do 365 { 366 status = max_write(MAX_REG_HXFR, MAX_HXFR_HS | (out ? MAX_HXFR_OUTNIN : 0)); 367 status = max_wait_transfer(status); 368 hrsl = max_read(MAX_REG_HRSL, &status); 369 } 370 while (hrsl & MAX_HRSL_HRSLT); 371 372 return status; 373 } 374 375 /** 376 * Send a request to the given address and endpoint, using the supplied data 377 * payload with the given length, indicating the preserved toggle state of the 378 * endpoint (which will be updated). 379 */ 380 uint8_t max_send(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t len, bool *toggle) 381 { 382 uint8_t status, hrsl = 0; 383 384 max_write_fifo(endpoint, data, len); 385 386 if (endpoint) 387 max_set_send_toggle(*toggle); 388 389 /* Set the address. */ 390 391 max_write(MAX_REG_PERADDR, address); 392 393 /* Initiate the transfer. */ 394 395 do 396 { 397 status = max_write(MAX_REG_HXFR, endpoint | MAX_HXFR_OUTNIN); 398 status = max_wait_transfer(status); 399 400 /* Test for usable data. */ 401 402 if (!(status & MAX_HIRQ_SNDBAVIRQ)) 403 continue; 404 405 hrsl = max_read(MAX_REG_HRSL, &status); 406 } 407 while (hrsl & MAX_HRSL_HRSLT); 408 409 if (endpoint) 410 *toggle = max_get_send_toggle(); 411 412 return status; 413 } 414 415 /** 416 * Make a request for data from the given address and endpoint, collecting it in 417 * the supplied buffer with the given length, indicating the preserved toggle 418 * state of the endpoint (which will be updated) The length will be updated to 419 * indicate the total length of the received data. 420 */ 421 uint8_t max_recv(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t *len, bool *toggle) 422 { 423 uint8_t *datalimit = data + *len; 424 uint8_t status, hrsl = 0; 425 426 if (endpoint) 427 max_set_send_toggle(*toggle); 428 429 /* Set the address. */ 430 431 max_write(MAX_REG_PERADDR, address); 432 433 /* Initiate the transfer. */ 434 435 do 436 { 437 status = max_write(MAX_REG_HXFR, endpoint); 438 status = max_wait_transfer(status); 439 440 /* Test for usable data. */ 441 442 if (!(status & MAX_HIRQ_RCVDAVIRQ)) 443 continue; 444 445 hrsl = max_read(MAX_REG_HRSL, &status); 446 } 447 while (hrsl & MAX_HRSL_HRSLT); 448 449 do 450 { 451 max_read_fifo(data, len, datalimit); 452 453 /* Indicate that all data has been read. */ 454 455 status = max_write(MAX_REG_HIRQ, MAX_HIRQ_RCVDAVIRQ); 456 } 457 while (status & MAX_HIRQ_RCVDAVIRQ); 458 459 if (endpoint) 460 *toggle = max_get_send_toggle(); 461 462 return status; 463 } 464 465 void chipreset() 466 { 467 printf("Resetting...\n"); 468 max_write(MAX_REG_USBCTL, MAX_USBCTL_CHIPRES); 469 470 printf("Clearing the reset...\n"); 471 max_write(MAX_REG_USBCTL, 0); 472 } 473 474 uint8_t check() 475 { 476 uint8_t oscillator; 477 478 oscillator = max_read(MAX_REG_USBIRQ, NULL); 479 480 return (oscillator & ~(MAX_USBIRQ_NOVBUSIRQ | MAX_USBIRQ_VBUSIRQ)) == MAX_USBIRQ_OSCOKIRQ; 481 } 482 483 uint8_t wait() 484 { 485 uint16_t timeout = 1024; 486 487 /* Wait for the oscillator before performing USB activity. */ 488 489 printf("Waiting...\n"); 490 491 while ((timeout > 0) && (!check())) 492 { 493 timeout--; 494 } 495 496 printf("Iterations remaining: %d\n", timeout); 497 498 return timeout; 499 } 500 501 /** 502 * Return whether the bus is ready to be sampled. The application note claims 503 * that the SAMPLEBUS bit is cleared, but this does not seem to be the case. 504 */ 505 uint8_t samplebusready() 506 { 507 uint8_t result; 508 509 result = max_read(MAX_REG_HCTL, NULL); 510 return result & MAX_HCTL_SAMPLEBUS; 511 } 512 513 void samplebus() 514 { 515 max_write(MAX_REG_HCTL, MAX_HCTL_SAMPLEBUS); 516 while (!samplebusready()); 517 } 518 519 /** 520 * Handle the connection or disconnection of a device, returning true if the 521 * device is now connected or false otherwise. If the device is connected, a 522 * bus reset is performed. 523 */ 524 bool devicechanged() 525 { 526 uint8_t hrsl, mode; 527 528 hrsl = max_read(MAX_REG_HRSL, NULL); 529 mode = max_read(MAX_REG_MODE, NULL); 530 531 if ((hrsl & MAX_HRSL_JSTATUS) && (hrsl & MAX_HRSL_KSTATUS)) 532 { 533 printf("Bad device status.\n"); 534 } 535 else if (!(hrsl & MAX_HRSL_JSTATUS) && !(hrsl & MAX_HRSL_KSTATUS)) 536 { 537 printf("Device disconnected.\n"); 538 } 539 else 540 { 541 printf("Device connected.\n"); 542 543 /* Low speed device when J and lowspeed have the same level. 544 Since J and K should have opposing levels, K can be tested when 545 lowspeed is low. */ 546 547 if (((hrsl & MAX_HRSL_JSTATUS) && (mode & MAX_MODE_LOWSPEED)) || 548 ((hrsl & MAX_HRSL_KSTATUS) && !(mode & MAX_MODE_LOWSPEED))) 549 { 550 printf("Device is low speed.\n"); 551 max_write(MAX_REG_MODE, MAX_MODE_HOST_LOWSPEED); 552 } 553 else 554 { 555 printf("Device is full speed.\n"); 556 max_write(MAX_REG_MODE, MAX_MODE_HOST_FULLSPEED); 557 } 558 559 /* Reset the device. */ 560 561 max_write(MAX_REG_HCTL, MAX_HCTL_BUSRST); 562 return true; 563 } 564 565 return false; 566 } 567 568 void setup_packet(uint8_t *setup, uint8_t request_type, uint8_t request, uint16_t value, uint16_t index, uint16_t length) 569 { 570 setup[0] = request_type; 571 setup[1] = request; 572 setup[2] = value & 0xff; 573 setup[3] = value >> 8; 574 setup[4] = index & 0xff; 575 setup[5] = index >> 8; 576 setup[6] = length & 0xff; 577 setup[7] = length >> 8; 578 } 579 580 bool max_init_device(max_device *device) 581 { 582 uint8_t data[64], len = 64, setup[8]; 583 584 printf("Sending control request to address 0, endpoint 0...\n"); 585 setup_packet(setup, USB_ENDPOINT_IN, USB_REQ_GET_DESCRIPTOR, USB_DT_DEVICE, 0, USB_DT_DEVICE_SIZE); 586 max_control(0, setup); 587 max_recv(0, 0, data, &len, &device->in_toggle); 588 max_control_status(true); 589 590 if (len >= sizeof(struct usb_device_descriptor)) 591 { 592 memcpy(&device->desc, data, sizeof(struct usb_device_descriptor)); 593 printf("bLength: %d\n", device->desc.bLength); 594 printf("bDescriptorType: %d\n", device->desc.bDescriptorType); 595 printf("bcdUSB: %d\n", device->desc.bcdUSB); 596 printf("bDeviceClass: %d\n", device->desc.bDeviceClass); 597 printf("bDeviceSubClass: %d\n", device->desc.bDeviceSubClass); 598 printf("bDeviceProtocol: %d\n", device->desc.bDeviceProtocol); 599 printf("bMaxPacketSize0: %d\n", device->desc.bMaxPacketSize0); 600 printf("idVendor: %x\n", device->desc.idVendor); 601 printf("idProduct: %x\n", device->desc.idProduct); 602 printf("bcdDevice: %d\n", device->desc.bcdDevice); 603 printf("iManufacturer: %d\n", device->desc.iManufacturer); 604 printf("iProduct: %d\n", device->desc.iProduct); 605 printf("iSerialNumber: %d\n", device->desc.iSerialNumber); 606 printf("bNumConfigurations: %d\n", device->desc.bNumConfigurations); 607 608 /* Reset the device. */ 609 610 max_write(MAX_REG_HCTL, MAX_HCTL_BUSRST); 611 return true; 612 } 613 614 return false; 615 } 616 617 void shutdown(int signum) 618 { 619 printf("Closing...\n"); 620 ubb_close(0); 621 exit(1); 622 } 623 624 int main(int argc, char *argv[]) 625 { 626 uint8_t status = 0, revision = 0; 627 uint16_t count; 628 bool bus_event, data_event, suspended_event, connection_event, frame_event; 629 max_device device; 630 max_devstate devstate = MAX_DEVSTATE_INIT; 631 632 device.in_toggle = false; 633 device.out_toggle = false; 634 635 signal(SIGINT, &shutdown); 636 637 if (ubb_open(0) < 0) { 638 perror("ubb_open"); 639 return 1; 640 } 641 642 ubb_power(1); 643 printf("Power on.\n"); 644 645 OUT(MAX_SS); 646 OUT(MAX_MOSI); 647 OUT(MAX_SCLK); 648 OUT(MAX_RESET); 649 IN(MAX_INT); 650 IN(MAX_MISO); 651 652 /* Initialise SPI. */ 653 /* Set SS# to 1. */ 654 655 SET(MAX_SS); 656 CLR(MAX_MOSI); 657 CLR(MAX_SCLK); 658 SET(MAX_RESET); 659 660 /* Initialise the MAX3421E. */ 661 662 /* Set full-duplex, interrupt signalling. */ 663 664 printf("Setting pin control...\n"); 665 max_write(MAX_REG_PINCTL, MAX_PINCTL_INTLEVEL_LEVEL | MAX_PINCTL_FDUPSPI_FULL); 666 667 chipreset(); 668 printf("Ready? %d\n", wait()); 669 670 /* Check various registers. */ 671 672 printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); 673 printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); 674 675 /* Set host mode. */ 676 677 printf("Setting mode...\n"); 678 status = max_write(MAX_REG_MODE, MAX_MODE_HOST_ENABLED); 679 680 printf("Setting INT signalling...\n"); 681 status = max_write(MAX_REG_CPUCTL, MAX_CPUCTL_IE); 682 683 printf("Setting event signalling...\n"); 684 status = max_write(MAX_REG_HIEN, MAX_HIEN_CONDETIE | MAX_HIEN_FRAMEIE | MAX_HIEN_BUSEVENTIE); 685 686 /* Check various registers. */ 687 688 printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); 689 printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); 690 printf("IE: %x\n", max_read(MAX_REG_HIEN, &status)); 691 printf("CPU: %x\n", max_read(MAX_REG_CPUCTL, &status)); 692 printf("Pin: %x\n", max_read(MAX_REG_PINCTL, &status)); 693 printf("USBIRQ: %x\n", max_read(MAX_REG_USBIRQ, &status)); 694 printf("USBIE: %x\n", max_read(MAX_REG_USBIEN, &status)); 695 696 /* Read from the REVISION register. */ 697 698 printf("Reading...\n"); 699 revision = max_read(MAX_REG_REVISION, &status); 700 printf("Revision = %x\n", revision); 701 702 /* Sample the bus for any devices that are already connected. */ 703 704 samplebus(); 705 706 if (devicechanged()) 707 { 708 devstate = MAX_DEVSTATE_CONNECTED; 709 } 710 711 /* Enter the main processing loop. */ 712 713 for (count = 0; count <= 65535; count++) 714 { 715 if (!PIN(MAX_INT)) 716 { 717 /* Obtain interrupt conditions. */ 718 719 status = max_read(MAX_REG_HIRQ, NULL); 720 721 bus_event = status & MAX_HIRQ_BUSEVENTIRQ; 722 data_event = status & MAX_HIRQ_RCVDAVIRQ; 723 suspended_event = status & MAX_HIRQ_SUSDNIRQ; 724 connection_event = status & MAX_HIRQ_CONDETIRQ; 725 frame_event = status & MAX_HIRQ_FRAMEIRQ; 726 727 #ifdef DEBUG 728 if (bus_event) printf("Bus "); 729 if (data_event) printf("Data "); 730 if (suspended_event) printf("Suspended "); 731 if (connection_event) printf("Connection "); 732 if (frame_event) printf("Frame "); 733 printf("\n"); 734 #endif 735 736 /* Acknowledge the interrupts. */ 737 738 max_write(MAX_REG_HIRQ, status); 739 740 /* Detect device connection/disconnection. */ 741 742 if ((devstate == MAX_DEVSTATE_INIT) && connection_event && devicechanged()) 743 { 744 devstate = MAX_DEVSTATE_CONNECTED; 745 printf("CONNECTED\n"); 746 } 747 748 /* Handle device reset initiation. */ 749 750 else if ((devstate == MAX_DEVSTATE_CONNECTED) && bus_event) 751 { 752 max_write(MAX_REG_MODE, max_read(MAX_REG_MODE, NULL) | MAX_MODE_SOFKAENAB); 753 devstate = MAX_DEVSTATE_RESET; 754 printf("RESET\n"); 755 } 756 757 /* Handle device reset completion, getting device details and 758 initiating a second reset. */ 759 760 else if ((devstate == MAX_DEVSTATE_RESET) && frame_event && max_can_send(&status)) 761 { 762 max_init_device(&device); 763 devstate = MAX_DEVSTATE_INSPECTED; 764 printf("INSPECTED\n"); 765 } 766 767 /* Handle the second device reset initiation. */ 768 769 else if ((devstate == MAX_DEVSTATE_INSPECTED) && bus_event) 770 { 771 devstate = MAX_DEVSTATE_RESET_AGAIN; 772 printf("RESET AGAIN\n"); 773 } 774 775 /* Handle the second device reset completion, initiating communications. */ 776 777 else if ((devstate == MAX_DEVSTATE_RESET_AGAIN) && frame_event && max_can_send(&status)) 778 { 779 max_write(MAX_REG_MODE, max_read(MAX_REG_MODE, NULL) & ~MAX_MODE_SOFKAENAB); 780 devstate = MAX_DEVSTATE_READY; 781 printf("READY\n"); 782 } 783 784 /* Handle device disconnection. */ 785 786 else if ((devstate != MAX_DEVSTATE_INIT) && connection_event) 787 { 788 devstate = MAX_DEVSTATE_INIT; 789 printf("INIT\n"); 790 } 791 } 792 } 793 794 printf("Closing...\n"); 795 ubb_close(0); 796 797 return 0; 798 }